coreboot/src/cpu/x86
Patrick Georgi ce2564ac51 smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG
This mitigates the Memory Sinkhole issue (described on
https://github.com/xoreaxeaxeax/sinkhole) by checking for the issue and
crashing the system explicitly if LAPIC overlaps ASEG.
This needs to happen without a data access (only code fetches) because
data accesses could be tampered with.

Don't try to recover because, if somebody tried to do shenanigans like
these, we have to expect more.
Sandybridge is safe because it does the same test in hardware, and
crashes. Newer chipsets presumably do the same.

This needs to be extended to deal with overlapping TSEG as well.

Change-Id: I508c0b10ab88779da81d18a94b08dcfeca6f5a6f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/11519
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
2015-10-29 10:27:00 +01:00
..
16bit x86/bootblock: Use LDFLAGS_bootblock to enable garbage collection 2015-10-07 03:08:58 +00:00
32bit x86: link romstage like the other architectures 2015-09-09 19:35:12 +00:00
cache post code: Replaced hard-coded post code with macro 2012-01-23 22:50:56 +01:00
lapic x86: add standalone verstage support 2015-10-14 17:07:52 +00:00
mtrr cpu/x86/mtrr: Add MTRR index and total MTRRs to error message 2015-10-15 23:31:38 +00:00
name Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
pae cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false 2014-06-29 13:02:13 +02:00
smm smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG 2015-10-29 10:27:00 +01:00
tsc x86: add standalone verstage support 2015-10-14 17:07:52 +00:00
car.c amd: raminit sysinfo offset fix 2015-08-13 16:10:17 +02:00
fpu_enable.inc Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
Kconfig smmhandler: on i945..nehalem, crash if LAPIC overlaps with ASEG 2015-10-29 10:27:00 +01:00
Makefile.inc rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
mirror_payload.c x86: fix mirror_payload() 2015-06-02 14:09:47 +02:00
mp_init.c cpu/mtrr.h: Fix macro names for MTRR registers 2015-10-15 03:52:49 +00:00
sipi_vector.S rmodule: use program.ld for linking 2015-09-09 19:35:30 +00:00
sse_enable.inc Remove empty lines at end of file 2015-06-08 00:55:07 +02:00