coreboot/src/vendorcode
Zheng Bao 5c59fefd89 Cezanne FSP wrapper: Sync with PI 1.0.0.5
New PI 1.0.0.5 has more data in HOB of DMI, which has been uploaded to
google internal repo. The dismatched size of HOB causes the wrong data
tranfer. So the coreboot also need to change.

BUG=b:204732649

Change-Id: Id95c37a0d7027d75afddf9d7528ff41ae3a347f5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-30 15:50:11 +00:00
..
amd Cezanne FSP wrapper: Sync with PI 1.0.0.5 2021-11-30 15:50:11 +00:00
cavium src: use ARRAY_SIZE where possible 2021-02-15 11:30:40 +00:00
eltan src/vendorcode/eltan: Don't reference CONFIG_CBFS_SIZE 2021-07-28 08:19:30 +00:00
google ChromeOS: Fix <vc/google/chromeos/chromeos.h> 2021-11-09 00:14:46 +00:00
intel vendorcode/intel/fsp: Add Alder Lake FSP headers for FSP v2422_01 2021-11-15 09:57:35 +00:00
mediatek vc/mediatek/mt8195: Remove unused code and comments 2021-11-01 15:57:11 +00:00
siemens cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
Makefile.inc soc/mediatek/mt8192: initialize DRAM using vendor reference code 2021-03-08 03:15:43 +00:00