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Aaron Durbin 5c48b7e9f2 soc/intel/skylake: remove unused SMI functions 
The southbridge_trigger_smi() and southbridge_clear_smi_status()
functions are unused. Remove them.

Change-Id: I86994191a63cbf515bc330433ef7c3f79a39936e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-05-08 06:10:25 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch arch/x86: Share storage data structures between early stages 2017-05-01 17:37:59 +02:00
commonlib commonlib: Add ID for STORAGE_DATA 2017-04-28 19:56:11 +02:00
console console: rework log level to not be reliant on ROMSTAGE_CONST 2017-04-25 18:13:56 +02:00
cpu nb/amd/amdk8: Link reset_test.c 2017-04-28 17:17:40 +02:00
device lib/edid.c: Allow use of when not NGI 2017-05-03 16:16:32 +02:00
drivers drivers/intel/wifi: provide weak get_wifi_sar_limits() 2017-05-08 06:09:56 +02:00
ec ec/google/chromeec: provide reboot function 2017-05-05 23:23:58 +02:00
include drivers/spi: Re-factor spi_crop_chunk 2017-05-05 23:42:19 +02:00
lib lib/edid: Save the display ASCII string 2017-05-03 16:18:15 +02:00
mainboard mb/google/reef: enable SAR and DSAR 2017-05-08 06:10:12 +02:00
northbridge nb/intel/sandybridge/early_init: Use register name 2017-05-05 23:23:16 +02:00
soc soc/intel/skylake: remove unused SMI functions 2017-05-08 06:10:25 +02:00
southbridge drivers/spi: Re-factor spi_crop_chunk 2017-05-05 23:42:19 +02:00
superio superio/fintek: Add support for Fintek F71808A 2017-03-27 19:19:56 +02:00
vboot vboot: Separate board name and version number in FWID with a dot 2017-04-29 01:44:10 +02:00
vendorcode cr50: check if the new image needs to be enabled and act on it 2017-05-05 23:24:20 +02:00
Kconfig cr50: check if the new image needs to be enabled and act on it 2017-05-05 23:24:20 +02:00