Kyösti Mälkki 59e0334207 AGESA: Switch to MMCONF_SUPPORT_DEFAULT ... Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2016-12-01 05:49:09 +01:00
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allwinner	cpu/allwinner/a10/uart_console.c: Init new serial struct variables	2016-11-24 00:06:47 +01:00
amd	AGESA: Switch to MMCONF_SUPPORT_DEFAULT	2016-12-01 05:49:09 +01:00
armltd	vboot2: add verstage	2015-01-27 01:41:40 +01:00
dmp	src/cpu: Improve code formatting	2016-09-04 05:33:04 +02:00
intel	intel sandy/ivy: Increase XIP cache with USE_NATIVE_RAMINIT	2016-11-20 21:21:36 +01:00
qemu-power8	cpu/qemu-power8: don't enable it for qemu-x86	2016-02-19 20:03:52 +01:00
qemu-x86	qemu-x86: Enable SMP support	2015-12-08 15:54:27 +01:00
ti	Kconfig: lay groundwork for not assuming SPI flash boot device	2016-08-18 06:18:21 +02:00
via	src/cpu: Remove unnecessary whitespace	2016-10-07 18:08:25 +02:00
x86	cpu/x86/mtrr: allow temporary MTRR range during coreboot	2016-11-12 04:06:33 +01:00
Kconfig	Kconfig: Add option for microcode filenames	2016-09-08 00:29:08 +02:00
Makefile.inc	src/cpu: Fix location for cpu_microcode_blob.bin in COREBOOT CBFS only	2016-10-11 23:36:18 +02:00