coreboot/src/northbridge
Patrick Rudolph 8d120a532b UPSTREAM: device/dram/ddr2: Add common ddr2 spd decoder
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.

Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.

BUG=none
BRANCH=none
TEST=none

Change-Id: I2580a164627a0348da02aad6dbbe5311c442fe35
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6e53ae6f5c
Original-Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/18273
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Original-Tested-by: build bot (Jenkins)
Reviewed-on: https://chromium-review.googlesource.com/452895
2017-03-10 10:54:48 -08:00
..
amd UPSTREAM: AGESA: Fix loop condition for eventlog read 2017-03-10 10:54:36 -08:00
intel UPSTREAM: northbridge/intel/i440bx: Align code 2017-03-10 10:54:45 -08:00
via UPSTREAM: device/dram/ddr2: Add common ddr2 spd decoder 2017-03-10 10:54:48 -08:00