coreboot/src/drivers/intel
Brandon Breitenstein 591c727997 UPSTREAM: fsp2_0: implement stage cache for silicon init
Stage cache will save ~20ms on S3 resume for apollolake platforms.
Implementing the cache in ramstage to save silicon init and reload
it on resume. This patch adds passing S3 status to silicon init in
order to verify that the wake is from S3 and not for some other
reason. This patch also includes changes needed for quark and
skylake platforms that require fsp 2.0.

BUG=chrome-os-partner:56941
BRANCH=none
TEST=built for reef and tested boot and S3 resume path saving 20ms

Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/17460
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: I99dc93c1d7a7d5cf8d8de1aa253a326ec67f05f6
Reviewed-on: https://chromium-review.googlesource.com/414562
Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-29 17:38:17 -08:00
..
fsp1_0 UPSTREAM: src/drivers: Add required space before opening parenthesis '(' 2016-09-04 19:36:54 -07:00
fsp1_1 UPSTREAM: intel post-car: Increase stacktop alignment 2016-11-21 11:53:20 -08:00
fsp2_0 UPSTREAM: fsp2_0: implement stage cache for silicon init 2016-11-29 17:38:17 -08:00
gma UPSTREAM: src/drivers: Remove whitespace after memcpy & memset 2016-10-11 14:31:40 -07:00
i210 UPSTREAM: intel/i210: Change API for function mainboard_get_mac_address() 2016-07-07 01:09:39 -07:00
wifi UPSTREAM: drivers/intel/wifi: Add depends on ARCH_X86 2016-10-11 14:32:10 -07:00