Raul E Rangel 58a8ad1661 soc/amd: Move root complex SSDT TOM1/TOM2 generation function ... This will also be used for cezanne. Stoney also has a similar function, but it hard codes the scope path. I didn't have a device setup to test if switching to this function was a no-op. So I left it. TOM2 isn't used by any ASL, so we could remove it later. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2021-02-22 07:29:19 +00:00
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cezanne	soc/amd/cezanne/acpi/soc.asl: Add platform.asl	2021-02-22 07:29:09 +00:00
common	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
picasso	soc/amd: Move root complex SSDT TOM1/TOM2 generation function	2021-02-22 07:29:19 +00:00
stoneyridge	ACPI: Use common OperationRegion for PCI_MMCONF	2021-02-20 21:38:54 +00:00
Kconfig