Julian Schroeder 577e146895 soc/amd/cezanne: add ACPI CPPC support for AMD ... This leverages the existing Collaborative Processor Performance Control (CPPC) support and adds CPPC init for AMD/Cezanne. BUG=b:185814875 TEST=under Linux/ChromeOS, acpidump ssdt2, find expected CPPC entries Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com> Change-Id: I94172f40c7fa4b7b89237fd382448e598da00fbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/56188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2021-07-15 21:39:04 +00:00
..
amd	soc/amd/cezanne: add ACPI CPPC support for AMD	2021-07-15 21:39:04 +00:00
cavium
example	src: Introduce ARCH_ALL_STAGES_X86	2021-07-02 08:19:10 +00:00
intel	soc/intel/alderlake: Add virtual GPIOs for community 1	2021-07-15 14:07:20 +00:00
mediatek	soc/mediatek/mt8195: Get DRAM size from DRAM calibration result	2021-07-14 09:47:39 +00:00
nvidia
qualcomm	sc7280: Add target specific GPIO pin definitions	2021-06-11 07:36:16 +00:00
rockchip
samsung
sifive
ti
ucb