coreboot/src/soc
Raul E Rangel 9882dde03f soc/amd/picasso: Generate GNB IO-APIC PCI routing table
This adds support for generating a PCI routing table that routes to the
GNB IO-APIC. This means we no longer need to route to the FCH IO-APIC
for PCI interrupts.

BUG=b:170595019
TEST=Boot ezkinil to OS with `pci=nomsi amd_iommu=off` and verify
all peripherals are working

           CPU0       CPU1
  0:        112          0   IO-APIC   2-edge      timer
  1:          0         99   IO-APIC   1-edge      i8042
  4:          0       2523   IO-APIC   4-edge      ttyS0
  5:      34632          0   IO-APIC   5-fasteoi   mmc1
  7:       5646          0   IO-APIC   7-fasteoi   pinctrl_amd
  8:          0          0   IO-APIC   8-edge      rtc0
  9:          0         33   IO-APIC   9-fasteoi   acpi
 10:      88258          0   IO-APIC  10-edge      AMD0010:00
 11:          0      32485   IO-APIC  11-edge      AMD0010:01
 24:       3301          0  amd_gpio   3  cr50_i2c
 25:          0     235214   IO-APIC  28-fasteoi   amdgpu
 26:      67408          0   IO-APIC  31-fasteoi   xhci-hcd:usb1
 27:          0     488876   IO-APIC   8-fasteoi   mmc0
 28:       1265          0  amd_gpio   9  PNP0C50:00
 29:        656          0  amd_gpio  12  ELAN9004:00
 30:        413          0  amd_gpio  31  chromeos-ec
 31:      14153          0   IO-APIC   4-fasteoi   ath10k_pci
 32:          2          0  sysfstrig0      cros-ec-accel_consumer3
 33:          2          0  sysfstrig0      cros-ec-accel_consumer0
 34:          6          0  amd_gpio  62  rt5682
 35:          0      38937   IO-APIC  29-fasteoi   snd_hda_intel:card0, ACP3x_I2S_IRQ

Cq-Depend: chrome-internal:3452710
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3211ab351a332fafb7b5f9ef486bb6646d9a214c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-01-08 08:12:53 +00:00
..
amd soc/amd/picasso: Generate GNB IO-APIC PCI routing table 2021-01-08 08:12:53 +00:00
cavium cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
example arch/x86: Move prologue to .init section 2021-01-07 11:02:03 +00:00
intel */Makefile.inc: Add some INTERMEDIATE targets to .PHONY 2021-01-08 08:08:07 +00:00
mediatek soc/mediatek: rtc: Use bool as return type 2021-01-07 02:02:51 +00:00
nvidia Makefile: Add $(xcompile) to specify where to write xcompile 2020-12-23 03:40:35 +00:00
qualcomm cbfs: Simplify load/map API names, remove type arguments 2020-12-02 22:13:17 +00:00
rockchip drivers: Replace set_vbe_mode_info_valid 2020-12-17 06:21:56 +00:00
samsung cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
sifive cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ti cbfs: Enable CBFS mcache on most chipsets 2020-12-02 22:12:10 +00:00
ucb soc/ucb/riscv: Add chip_operations stub 2020-05-28 09:30:35 +00:00