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coreboot/src/soc
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Aaron Durbin 64606cea93 soc/intel/skylake: don't hardcode GPE0 standard reg 
While using '3' is fine for the standard gpe0 for skylake, I want
to make sure anyone that copies this code doesn't tweak GPE0_REG_MAX
without the hard coded index. If that does happen now things will
still work, but it may just not match the hardware proper.

BUG=chrome-os-partner:58666

Change-Id: I434b9a765a0a2f263490bb2b4ecb3635292d46c9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17160
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-28 19:01:48 +02:00
..
broadcom/cygnus soc/broadcom/cygnus/ddr_init.c: Correct typo in POWER ON and POWER OK. 2016-08-31 20:23:34 +02:00
dmp/vortex86ex src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
imgtec/pistachio drivers/uart: Use uart_platform_refclk for all UART models 2016-05-09 18:45:44 +02:00
intel soc/intel/skylake: don't hardcode GPE0 standard reg 2016-10-28 19:01:48 +02:00
lowrisc/lowrisc riscv: add the lowrisc System On Chip support 2016-10-25 22:31:06 +02:00
marvell marvell/mvmap2315: Compose BOOTBLOCK region 2016-10-21 19:42:23 +02:00
mediatek/mt8173 src/soc: Add required space before opening parenthesis '(' 2016-08-31 20:09:42 +02:00
nvidia Makefiles: update cbfs types from bare numbers to values 2016-09-21 09:36:11 +02:00
qualcomm soc/qualcomm/ipq40xx: Fix GPIO pull up config. 2016-10-07 17:55:19 +02:00
rdc/r8610 rdc/r8610: Move to src/soc 2016-05-05 20:08:58 +02:00
rockchip rockchip/rk3399: reset system if DDR init fails 2016-10-25 17:08:58 +02:00
samsung src/soc: Capitalize CPU, ACPI, RAM and ROM 2016-07-31 19:27:53 +02:00
ucb/riscv soc/ucb/riscv: select BOOTBLOCK_CONSOLE 2016-08-15 18:24:42 +02:00