coreboot/src
Duncan Laurie 556321167f CPU: Add option to set TCC activation offset
The default TCC activation offset is 0, which means TCC
activation starts at Tj_max.  For devices with limited
cooling ability it may be desired to lower TCC activation.

This adds an option that can be declared in the devicetree
to set the TCC activation to a non-zero value.

Enable tcc_offset=15 in devicetree.cb and build/boot
the BIOS and check that the value is set in the MSR:

> and $(shr $(rdmsr 0 0x1a2) 24) 0xf
0xf

Change-Id: I88f6857b40fd354f70fa9d5d9c1d8ceaea6dfcd1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1343
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-26 20:32:45 +02:00
..
arch/x86 ACPI: Add function to write _PPC using NVS 2012-07-26 20:31:52 +02:00
boot Implement stack overflow checking for the BSP 2012-07-24 23:29:12 +02:00
console USBDEBUG: buffer up to 8 bytes 2012-07-26 15:52:00 +02:00
cpu CPU: Add option to set TCC activation offset 2012-07-26 20:32:45 +02:00
devices Remove useless semicolon 2012-07-25 12:26:33 +02:00
drivers Remove copies of rtl8168.c 2012-07-26 19:02:59 +02:00
ec Add EC component for SMSC MEC1308/1310 2012-04-02 18:42:40 +02:00
include USBDEBUG: buffer up to 8 bytes 2012-07-26 15:52:00 +02:00
lib USBDEBUG: buffer up to 8 bytes 2012-07-26 15:52:00 +02:00
mainboard Add correct bios callout into read event routine 2012-07-26 19:10:27 +02:00
northbridge Change multiply ONE_MB to bit shifting. 2012-07-25 22:15:17 +02:00
southbridge NVS: Add a temp sensor ID and an ACPI Method to set it 2012-07-26 20:31:31 +02:00
superio servengines/pilot superio: add attribute unused 2012-07-09 12:36:02 +02:00
vendorcode ELOG: Log events for Chrome OS developer/recovery mode 2012-07-25 22:24:56 +02:00
Kconfig Add an option for Waiting for gdb connection if the gdb stub configuration is chosen. 2012-06-23 07:50:07 +02:00
Kconfig.deprecated_options