coreboot/src/soc
Rizwan Qureshi 55597ff279 soc/intel/common: Add function to set BILD bit in RTC
Add a function to set the Bios Interface Lock Down bit (bit 31)
in RTC Configuration register (0x3400). This bit when set prevents
the top swap enable bit (bit 0) in the RTC BUC register (0x3414)
from being changed.

Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06 10:28:19 +00:00
..
amd chromeos/gnvs: remove function and naming cleanup 2018-09-06 10:26:50 +00:00
broadcom soc/broadcom/cygnus: Increase romstage SRAM size in memlayout 2018-08-13 12:16:32 +00:00
cavium soc/cn81xx: Add vboot support 2018-08-24 12:29:28 +00:00
imgtec soc/imgtec/pistachio: Get rid of device_t 2018-06-04 09:18:19 +00:00
intel soc/intel/common: Add function to set BILD bit in RTC 2018-09-06 10:28:19 +00:00
lowrisc riscv: add support for modifying compiler options 2018-07-17 18:09:43 +00:00
mediatek arm64: Factor out common parts of romstage execution flow 2018-08-17 21:29:46 +00:00
nvidia arm64: Remove set_cntfrq() function 2018-08-10 04:16:06 +00:00
qualcomm drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
rockchip drivers/i2c: Add i2c TPM support for different stages 2018-08-10 23:25:52 +00:00
samsung src: Fix typo 2018-08-10 21:25:53 +00:00
sifive riscv: separately define stack locations at different stages 2018-09-02 03:10:58 +00:00
ucb riscv: add support for modifying compiler options 2018-07-17 18:09:43 +00:00