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After DDR PHY reset de-asserted, DLL automatically starts to lock, and the lock time is maximum 5.12us. The output clock of DLL supplies the clocks of DDR controller and PHY digital logic. So before DLL lock, the clocks of DDR controller and PHY digital logic are indeterminate. When programming DDR in the period of DLL unlock, the programming maybe unstable because of the indeterminate clocks. So we need wait for at least 5.12us after de-asserting reset, then start to program DDR registers. Add some redundancy, the waiting time hopes to achieve 10us. BUG=chrome-os-partner:33148 TEST=I'm using the following command line test ok(15000 cycles). "while sleep 4 && dut-control cold_reset:on sleep:.1 cold_reset:off; do : ; done" BRANCH=None Change-Id: I55f8cb11ed3d7962567c5f40a31e6c8aed8fdcb0 Signed-off-by: DaiLunXue <dlx@rock-chips.com> Reviewed-on: https://chromium-review.googlesource.com/232894 Reviewed-by: Julius Werner <jwerner@chromium.org> Commit-Queue: Lunxue Dai <lunxue.dai@rock-chips.com> Tested-by: Lunxue Dai <lunxue.dai@rock-chips.com> |
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------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.