coreboot/src/security/intel
Angel Pons 2f1739ada8 security/intel/txt: Fix variable MTRR handling
The MSR macros were treated as memory addresses and the loops had
off-by-one errors. This resulted in a CPU exception before GETSEC, and
another exception after GETSEC (once the first exception was fixed).

Tested on Asrock B85M Pro4, ACM complains about the missing TPM and
resets the platform. When the `getsec` instruction is commented-out, the
board is able to boot normally, without any exceptions nor corruption.

Change-Id: Ib5d23cf9885401f3ec69b0f14cea7bad77eee19a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-08-07 11:56:29 +00:00
..
stm security/intel/stm: Add missing <stdbool.h> 2020-07-21 20:04:12 +00:00
txt security/intel/txt: Fix variable MTRR handling 2020-08-07 11:56:29 +00:00
Kconfig treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
Makefile.inc security/intel/stm: Add STM support 2020-02-05 18:49:27 +00:00