Patrick Georgi 42f15054b1 memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere ... This is in preparation of a larger heap. I went for 2MB because why not? Change-Id: I51f999a10ba894a7f2f5fce224d30bf914107c38 Signed-off-by: Patrick Georgi <patrick@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Julius Werner <jwerner@chromium.org>		2023-10-11 12:08:22 +00:00
..
include/soc
lp0
bootblock.c
bootblock_asm.S
cache.c
cbmem.c	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
chip.h
clock.c	soc/nvidia/tegra124: Fix building with clang	2022-11-10 15:33:32 +00:00
display.c
dma.c
dp.c	src/soc/nvidia: Remove unnecessary space after casts	2022-11-22 13:43:16 +00:00
i2c.c
Kconfig
maincpu.S
Makefile.inc	soc: Add SPDX license headers to Makefiles	2022-10-31 03:27:13 +00:00
memlayout.ld	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
monotonic_timer.c
power.c
sdram.c
sdram_lp0.c
soc.c	mb/qemu-i440fx,soc/nvidia: Fix coverity reported defects	2022-07-04 14:11:06 +00:00
sor.c	src/soc/nvidia: Remove unnecessary space after casts	2022-11-22 13:43:16 +00:00
spi.c
uart.c	lib/coreboot_table: Simplify API to set up lb_serial	2022-11-04 19:17:13 +00:00
verstage.c	soc/nvidia,qualcomm: Fix indirect includes	2021-11-09 00:13:25 +00:00