The STATESTS register is a very simple read/write-1-clear status
register. OS drivers have to read and clear it all the time with-
out any quirk handling. So it seems unlikely that this sequence
was ever necessary for any coreboot-supported chip.
More likely, that sequence was copied from the dance around the
reset bit when Poulsbo support was added in commit be61a17351
("Support Intel SCH (Poulsbo) and add iwave/iWRainbowG6 board
which uses it.").
TEST= Verbs were loaded correctly on off-tree HP ProBook 450 G3.
Change-Id: I1fbea8ffb71a2fcb4ce5f42b3cb8f816ec336c5b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89653
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
152914272c