Wonkyu Kim 528ae9e811 soc/tigerlake: Correct FSP log interface ... Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART. DEBUG_INTERFACE_UART: Legacy UART DEBUG_INTERFACE_SERIAL_IO: PCH UART BUG=None BRANCH=None TEST=Build with debug FSP and boot tglrvp boards and check FSP uart log Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I5374a5562ac56b305f57db10b1a61b297a4a1c67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/39167 Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-03-02 23:43:12 +00:00
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amd	soc/amd/picasso: Add PCI ID for Dali xHCI	2020-03-02 16:33:07 +00:00
cavium	soc/{amd,cavium,mediatek,sifive}: Remove unused <stdlib.h>	2019-12-19 05:38:43 +00:00
intel	soc/tigerlake: Correct FSP log interface	2020-03-02 23:43:12 +00:00
mediatek	treewide: capitalize 'USB'	2020-02-26 17:06:40 +00:00
nvidia	commonlib: Add commonlib/bsd	2020-01-28 06:36:13 +00:00
qualcomm	sc7180: clock: Fix QUP DFSR configuration for perf levels	2020-02-07 23:12:00 +00:00
rockchip	soc/rockchip: Fix typos	2020-02-24 13:04:02 +00:00
samsung	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
sifive	soc/{samsung,sifive}: Fix typos	2020-02-24 13:01:15 +00:00
ucb	mb/emulation/qemu-riscv: Implement ipi using clint to enable smp in qemu/spike.	2019-12-06 15:09:48 +00:00