Paul Menzel 526a46ed7e Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2 ... Commit »Support for the Intel ICH7 southbridge.« (debb11fc) [1] used `1 << 25` to set the I/O APIC ID of 2. Instead using `2 << 24`, which is the same value, makes it clear, that the I/O APIC ID is 2. Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID is 2« (8c937c7e) [2] is used as a template. [1] http://review.coreboot.org/gitweb?p=coreboot.git;a=commit;h=debb11fc1fe5f5560015ab9905f1ccc2e08c73e0 [2] http://review.coreboot.org/3100 Change-Id: Ib688500944cd78a1cc1c8082bb138fa9468bdbfb Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/3122 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2013-04-26 18:37:00 +02:00
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amd	AMD/SB800: Define the GPP PCIe lane distribution	2013-04-18 18:35:12 +02:00
broadcom	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
intel	Intel 82801gx: Use 2 << 24 to clarify that I/O APIC ID is 2	2013-04-26 18:37:00 +02:00
nvidia	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
rdc	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
ricoh	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	2013-03-01 10:16:08 +01:00
sis	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
ti	GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«	2013-03-01 10:16:08 +01:00
via	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
Kconfig	Add support for RDC R8610 Southbridge	2012-03-27 18:39:05 +02:00
Makefile.inc	Add support for RDC R8610 Southbridge	2012-03-27 18:39:05 +02:00