coreboot/src/northbridge/intel
Nicholas Chin 4320b5da8f nb/intel/gm45/northbridge.c: Use config_of_soc()
Use the config_of_soc macro, which resolves to a direct pointer to the
chip config, instead of the chip_info member of __pci_0_00_0 to obtain
the same address.

Change-Id: If265819613727853d0f96dc6bb95ba71a2cfeeb1
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-07 20:37:35 +00:00
..
common
e7505 cpu/x86: Make 1GB paging the default 2024-06-05 20:31:03 +00:00
gm45 nb/intel/gm45/northbridge.c: Use config_of_soc() 2024-10-07 20:37:35 +00:00
haswell nb/intel/*: Explicitly include static.h for config_of_soc 2024-10-07 20:32:33 +00:00
i440bx cbmem_top: Change the return value to uintptr_t 2024-07-10 12:55:46 +00:00
i945 nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00
ironlake nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00
pineview nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00
sandybridge nb/intel/*: Explicitly include static.h for config_of_soc 2024-10-07 20:32:33 +00:00
x4x nb/intel/*: Match ACPI with resource allocation 2024-08-05 08:28:44 +00:00