Duncan Laurie 51cb26d92a SMM: Fix state save map for sandybridge and TSEG ... There are enough differences that it is worth defining the proper map for the sandybridge/ivybridge CPUs. The state save map was not being addressed properly for TSEG and needs to use the right offset instead of pointing in ASEG. To do this properly add a required southbridge export to return the TSEG base and use that where appropriate. Change-Id: Idad153ed6c07d2633cb3d53eddd433a3df490834 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/1309 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2012-07-24 23:49:28 +02:00
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bist.h	We call this cache as ram everywhere, so let's call it the same in Kconfig	2010-08-30 17:53:13 +00:00
cache.h	Replace cache control magic numbers with symbols	2012-04-25 16:27:07 +02:00
car.h	Add infrastructure for global data in the CAR phase of boot	2012-03-29 23:19:13 +02:00
lapic.h	Use broadcast SIPI to startup siblings	2012-07-02 19:39:08 +02:00
lapic_def.h	Unify Local APIC address definitions	2012-03-08 15:39:05 +01:00
msr.h	remove trailing whitespace	2011-11-01 19:07:45 +01:00
mtrr.h	Intel cpus: Extend cache to cover complete Flash Device	2012-07-04 14:47:53 +02:00
multiboot.h	Generate multiboot tables from coreboot tables.	2010-09-13 14:47:22 +00:00
name.h	Factor out fill_processor_name() and strcpy() functions.	2010-09-29 09:54:16 +00:00
pae.h	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
post_code.h	Unify use of post_code	2011-04-11 20:17:22 +00:00
smm.h	SMM: Fix state save map for sandybridge and TSEG	2012-07-24 23:49:28 +02:00
stack.h	Since some people disapprove of white space cleanups mixed in regular commits	2010-04-27 06:56:47 +00:00
tsc.h	drop unneeded __ROMCC__ checks when the check for __PRE_RAM__ is more	2010-03-28 21:26:54 +00:00