coreboot/src/arch
Jonathan Neuschäfer a1e3924869 arch/riscv: Add missing "break;"
Change-Id: Iea3f12a5a7eb37586f5424db2d7a84c4319492f8
Reported-by: Coverity (1361947)
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16335
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-29 18:01:27 +02:00
..
arm src/arch: Add required space before opening parenthesis '(' 2016-08-28 18:48:30 +02:00
arm64 src/arch: Capitalize CPU and ACPI 2016-08-28 18:28:28 +02:00
mips build system: remove CBFSTOOL_PRE1_OPTS 2016-05-03 11:40:49 +02:00
power8 region: Add writeat and eraseat support 2016-06-24 20:48:12 +02:00
riscv arch/riscv: Add missing "break;" 2016-08-29 18:01:27 +02:00
x86 src/arch: Add required space before opening parenthesis '(' 2016-08-28 18:48:30 +02:00