coreboot/src/soc/intel
Johnny Lin 514930c2af soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
Processor attached memory should not use reserved_ram_from_to and
treat the calculation of gi_mem_size size as 64MB.

By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue. Before the fix running
command 'free -g -h' under Linux shows the total memory is only 1.4Gi,
after the fix it's showing the expected total memory size 15Gi.

Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.
On OCP Crater Lake with CXL memory attached, CXL memory can be recognized
in NUMA node 1:
numactl -H
available: 2 nodes (0-1)
node 0 cpus: 0 1 2 3 4 5 6 .. 59
node 0 size: 95854 MB
node 0 free: 93860 MB
node 1 cpus:
node 1 size: 63488 MB
node 1 free: 63488 MB
node distances:
node   0   1
  0:  10  14
  1:  14  10

Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-13 07:56:23 +00:00
..
alderlake Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" 2023-04-12 15:19:56 +00:00
apollolake soc/intel/apl: Fix programming temporary MTRR on GLK 2023-03-21 23:08:11 +00:00
baytrail arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminator 2023-02-09 16:54:11 +00:00
braswell treewide: Remove unuseful "_ADR: Address" comment 2023-02-17 15:41:37 +00:00
broadwell soc/intel/broadwell/gma: don't unconditionally remap all GPU PCI IDs 2023-03-09 16:57:07 +00:00
cannonlake soc/intel: Move USB PORTSC definition into IA common code 2023-03-26 19:44:15 +00:00
common Revert "soc/intel/rtd3: Hook up supported states to Kconfig" 2023-04-12 15:20:19 +00:00
denverton_ns arch/x86/include/cpu: introduce CPU_TABLE_END CPU table terminator 2023-02-09 16:54:11 +00:00
elkhartlake soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC Kconfig 2023-03-23 08:46:34 +00:00
jasperlake soc/intel/jsl: Select CSE defined ME spec version for jasperlake 2023-02-24 11:56:38 +00:00
meteorlake soc/intel/meteorlake: Perform feature control lock 2023-04-06 19:35:48 +00:00
quark tree: Move 'asmlinkage' before type 'void' 2023-02-27 00:34:18 +00:00
skylake soc/intel: Move USB PORTSC definition into IA common code 2023-03-26 19:44:15 +00:00
tigerlake Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT" 2023-04-12 15:19:56 +00:00
xeon_sp soc/intel/xeon_sp: Fix very small total memory when CXL is enabled 2023-04-13 07:56:23 +00:00
Makefile.inc soc: Add SPDX license headers to Makefiles 2022-10-31 03:27:13 +00:00