Chris Wang 50aa3d9921 soc/amd/mendocino: Remove the SPL DPTC parameter ... The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>		2023-03-04 02:28:45 +00:00
..
amd	soc/amd/mendocino: Remove the SPL DPTC parameter	2023-03-04 02:28:45 +00:00
cavium	treewide: Remove duplicated include <device/pci.h>	2023-02-01 03:03:34 +00:00
example/min86	soc: Add SPDX license headers to Makefiles	2022-10-31 03:27:13 +00:00
intel	xeon/spr: Set ACPI CPU string for 12bit	2023-03-04 02:11:01 +00:00
mediatek	soc/mediatek: Add config to control DRAM scramble	2023-03-02 09:24:11 +00:00
nvidia	treewide: stop calling custom TPM log "TCPA"	2023-01-11 16:00:55 +00:00
qualcomm	Revert "soc/qualcomm: Increase SPI frequency to 75 MHz"	2023-02-24 19:28:24 +00:00
rockchip	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
samsung	treewide: Fix old-style declarations	2023-01-17 04:23:49 +00:00
sifive/fu540	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00