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coreboot/src/cpu/intel
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Matt DeVillier 5ab732fa21 UPSTREAM: haswell: add CBMEM_MEMINFO table when initing RAM 
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.

On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.

Some values are hardcoded based on platform specifications.

BUG=none
BRANCH=none
TEST=none

Change-Id: I516cf6bb4b341743fea9110e300695d89aac92a2
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5aaa8ce21c
Original-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Original-Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Original-Reviewed-on: https://review.coreboot.org/19958
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/539221
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
2017-06-18 11:51:36 -07:00
..
car UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
common UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
ep80579 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
fit CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
fsp_model_206ax UPSTREAM: cpu/intel: Add int to unsigned 2017-03-16 11:25:44 -07:00
fsp_model_406dx UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
haswell UPSTREAM: haswell: add CBMEM_MEMINFO table when initing RAM 2017-06-18 11:51:36 -07:00
hyperthreading UPSTREAM: cpu/intel: Fix brace issues detected by checkpatch.pl 2017-03-16 11:25:45 -07:00
microcode UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
model_6bx UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_6dx UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
model_6ex UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
model_6fx UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
model_6xx UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_65x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_67x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_68x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_69x UPSTREAM: src/cpu/intel: Add license headers to all files 2017-02-26 05:40:57 -08:00
model_106cx UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
model_206ax UPSTREAM: cpu/intel/model_206ax: Use tsc monotonic timer 2017-06-12 14:15:54 -07:00
model_1067x UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
model_2065x UPSTREAM: Use more secure HTTPS URLs for coreboot sites 2017-06-12 08:47:49 -07:00
model_f0x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_f1x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_f2x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_f3x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
model_f4x UPSTREAM: src/cpu: Capitalize CPU, APIC and IOAPIC typo fix 2016-08-23 15:36:15 -07:00
slot_1 UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
slot_2 CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
smm/gen1 UPSTREAM: cpu/intel: Wrap lines at 80 columns 2017-03-16 11:25:45 -07:00
socket_441 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_BGA956 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_BGA1284 cpu/intel: Add socket BGA1284 2015-11-10 00:19:01 +01:00
socket_FC_PGA370 UPSTREAM: intel post-car: Split legacy sockets 2016-11-08 23:24:11 -08:00
socket_FCBGA559 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_LGA771 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_LGA775 UPSTREAM: cpu/intel/lga775: Do not select model_6ex CPU 2016-12-10 18:20:37 -08:00
socket_LGA1155 UPSTREAM: cpu/intel/model_206ax: Use tsc monotonic timer 2017-06-12 14:15:54 -07:00
socket_mFCBGA479 UPSTREAM: intel post-car: Split legacy sockets 2016-11-08 23:24:11 -08:00
socket_mFCPGA478 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_mPGA478 cpu: get rid of socket source code 2015-05-04 22:18:23 +02:00
socket_mPGA478MN UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_mPGA479M UPSTREAM: intel post-car: Split legacy sockets 2016-11-08 23:24:11 -08:00
socket_mPGA603 cpu: get rid of socket source code 2015-05-04 22:18:23 +02:00
socket_mPGA604 UPSTREAM: intel cache-as-ram: Move DCACHE_RAM_BASE 2016-12-19 09:55:24 -08:00
socket_PGA370 UPSTREAM: intel post-car: Split legacy sockets 2016-11-08 23:24:11 -08:00
socket_rPGA988B Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
socket_rPGA989 Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
speedstep UPSTREAM: cpu/intel: Fix the remaining issues detected by checkpatch 2017-03-16 11:25:46 -07:00
thermal_monitoring CPU/intel: Add missing license headers 2016-02-14 22:45:15 +01:00
turbo UPSTREAM: cpu/intel/turbo: Add option to disable turbo 2017-05-18 02:26:03 -07:00
Kconfig UPSTREAM: cpu/intel/common: Add/Use common function to set virtualization 2017-01-05 11:00:14 -08:00
Makefile.inc UPSTREAM: cpu/intel/socket_mPGA478MN: Add socket P 2016-11-08 23:24:32 -08:00