Aaron Durbin 4fa5fa5088 resources: introduce IORESOURCE_WRCOMB ... Certain MMIO resources can be set to a write-combining cacheable mode to increase performance. Typical resources that use this would be graphics memory. Change-Id: Icd96c720f86f7e2f19a6461bb23cb323124eb68e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/2891 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>		2013-03-29 19:54:08 +01:00
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agp.h
cardbus.h
device.h	resources: remove IORESOURCE_[UMA_FB|IGNORE_MTRR]	2013-03-29 19:54:00 +01:00
hypertransport.h
hypertransport_def.h
i2c.h	replace uchar and uint with standard types in generic i2c header	2013-02-06 02:11:38 +01:00
path.h	sconfig: rename lapic_cluster -> cpu_cluster	2013-02-14 07:07:20 +01:00
pci.h	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
pci_def.h	Add support for enabling PCIe Common Clock and ASPM	2012-03-29 22:16:07 +02:00
pci_ids.h	haswell: add PCI id support	2013-03-14 05:10:13 +01:00
pci_ops.h	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
pci_rom.h
pciexp.h	Add support for enabling PCIe Common Clock and ASPM	2012-03-29 22:16:07 +02:00
pcix.h
pnp.h	x86: Unify arch/io.h and arch/romcc_io.h	2013-03-22 00:00:09 +01:00
pnp_def.h
resource.h	resources: introduce IORESOURCE_WRCOMB	2013-03-29 19:54:08 +01:00
smbus.h
smbus_def.h