coreboot/src
Kevin Chang 4ed4c2474b mb/google/volteer/variant/lindar: Enable SA GV setting
Allow MRC training in SA GV.

BUG=b:177779469
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Idc9f634135b489450f53f8cd28d80649309d0f70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-01-21 11:03:35 +00:00
..
acpi ACPI: Refactor ChromeOS specific ACPI GNVS 2021-01-18 18:02:27 +00:00
arch ach/x86/postcar.c: Avoid double CBMEM initialization 2021-01-21 11:03:04 +00:00
commonlib drivers/tpm: Implement full PPI 2020-12-21 02:38:20 +00:00
console lib/trace: Remove TRACE support 2020-12-02 23:35:58 +00:00
cpu cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE 2021-01-21 09:08:14 +00:00
device device/oprom/x86emu/sys.c: Use __func__ 2021-01-18 09:44:02 +00:00
drivers drivers/intel/fsp1_1/temp_ram_exit.c: Initialize CBMEM 2021-01-21 11:02:43 +00:00
ec ec/google/chromeec/ec_commands.h: Remove repeated word 2021-01-18 07:38:09 +00:00
include ACPI: Refactor ChromeOS specific ACPI GNVS 2021-01-18 18:02:27 +00:00
lib lib/device_tree.c: Remove repeated word 2021-01-18 07:38:49 +00:00
mainboard mb/google/volteer/variant/lindar: Enable SA GV setting 2021-01-21 11:03:35 +00:00
northbridge cpu/intel/socket_LGA775: Increase DCACHE_RAM_SIZE 2021-01-21 09:08:14 +00:00
security security/tpm/tss/tcg-1.2/tss.c: Use __func__ 2021-01-19 08:58:50 +00:00
soc soc/intel/quark: Add pwrs in <soc/nvs.h> 2021-01-21 11:01:23 +00:00
southbridge ACPI GNVS: Drop APIC, factor out MPEN 2021-01-20 09:24:35 +00:00
superio src/superio: trim and move Makefile.inc, instead use wildcard matches 2020-12-27 14:46:07 +00:00
vendorcode ACPI: Refactor ChromeOS specific ACPI GNVS 2021-01-18 18:02:27 +00:00
Kconfig Kconfig: Show console debug options if loglevel override is set 2020-12-11 15:58:24 +00:00