Arthur Heymans 0e93a6f184 arch/riscv: Add clang as supported architecture ... All emulated targets properly compile and boot to the same extent as with gcc. Change-Id: I11ddd9347c2638fb7c26cd4939aa96ff8ddd1e66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74571 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Daniel Maslowski <info@orangecms.org>		2023-06-11 19:25:34 +00:00
..
include	arch/risc/mcall.h: Make the stack pointer global	2023-06-11 19:23:02 +00:00
arch_timer.c
boot.c	cbfs: Rename TYPE_FIT to TYPE_FIT_PAYLOAD	2022-06-01 19:45:08 +00:00
bootblock.S
fit_payload.c	arch/{arm64,riscv}: Remove "CRIT: " from log messages	2022-11-17 13:28:48 +00:00
fp_asm.S
Kconfig	arch/riscv: Add clang as supported architecture	2023-06-11 19:25:34 +00:00
Makefile.inc	arch/riscv: Always build opensbi with GCC	2023-06-11 19:23:34 +00:00
mcall.c
misaligned.c	arch/riscv: Use 'enum cb_err'	2022-12-25 15:09:48 +00:00
misc.c
opensbi.c	3rdparty/opensbi: Update to latest ToT	2022-09-14 20:12:56 +00:00
payload.c
pmp.c
ramstage.S
romstage.c
sbi.c	commonlib: Substitude macro "__unused" in compiler.h	2022-07-14 23:08:09 +00:00
smp.c	arch/riscv: Fix some SMP related headers	2022-01-19 19:29:42 +00:00
tables.c
trap_handler.c	arch/riscv/trap_handler.c: Use new names for CSR	2023-04-21 20:12:42 +00:00
trap_util.S	arch/riscv/trap_handler.c: Use new names for CSR	2023-04-21 20:12:42 +00:00
virtual_memory.c