a93900be8d
The register indexes and bitfield masks were guarded by the UART8250 config options, but it might be (is) necessary to use them in a driver that is UART8250 like without actually using the 8250 driver itself. To avoid any name collision with other drivers, also change the constant prefix from UART_ to UART8250_. BUG=None TEST=Built for link, lumpy, pit, and nyan. With this and other changes, got bootblock serial output on nyan. BRANCH=None Change-Id: Ie606d9e0329132961c3004688176204a829569dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://chromium-review.googlesource.com/171336 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org>
147 lines
5.6 KiB
C
147 lines
5.6 KiB
C
/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef __UART8250_H__
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#define __UART8250_H__
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/* Data */
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#define UART8250_RBR 0x00
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#define UART8250_TBR 0x00
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/* Control */
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#define UART8250_IER 0x01
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#define UART8250_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART8250_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART8250_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART8250_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART8250_IIR 0x02
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#define UART8250_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART8250_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART8250_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART8250_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART8250_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART8250_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART8250_FCR 0x02
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#define UART8250_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART8250_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART8250_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART8250_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART8250_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART8250_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART8250_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART8250_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART8250_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define UART8250_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART8250_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define UART8250_LCR 0x03
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#define UART8250_LCR_WLS_MSK 0x03 /* character length select mask */
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#define UART8250_LCR_WLS_5 0x00 /* 5 bit character length */
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#define UART8250_LCR_WLS_6 0x01 /* 6 bit character length */
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#define UART8250_LCR_WLS_7 0x02 /* 7 bit character length */
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#define UART8250_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART8250_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define UART8250_LCR_PEN 0x08 /* Parity eneble */
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#define UART8250_LCR_EPS 0x10 /* Even Parity Select */
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#define UART8250_LCR_STKP 0x20 /* Stick Parity */
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#define UART8250_LCR_SBRK 0x40 /* Set Break */
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#define UART8250_LCR_BKSE 0x80 /* Bank select enable */
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#define UART8250_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART8250_MCR 0x04
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#define UART8250_MCR_DTR 0x01 /* DTR */
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#define UART8250_MCR_RTS 0x02 /* RTS */
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#define UART8250_MCR_OUT1 0x04 /* Out 1 */
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#define UART8250_MCR_OUT2 0x08 /* Out 2 */
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#define UART8250_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART8250_MCR_DMA_EN 0x04
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#define UART8250_MCR_TX_DFR 0x08
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#define UART8250_DLL 0x00
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#define UART8250_DLM 0x01
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/* Status */
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#define UART8250_LSR 0x05
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#define UART8250_LSR_DR 0x01 /* Data ready */
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#define UART8250_LSR_OE 0x02 /* Overrun */
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#define UART8250_LSR_PE 0x04 /* Parity error */
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#define UART8250_LSR_FE 0x08 /* Framing error */
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#define UART8250_LSR_BI 0x10 /* Break */
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#define UART8250_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART8250_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART8250_LSR_ERR 0x80 /* Error */
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#define UART8250_MSR 0x06
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#define UART8250_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART8250_MSR_RI 0x40 /* Ring Indicator */
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#define UART8250_MSR_DSR 0x20 /* Data Set Ready */
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#define UART8250_MSR_CTS 0x10 /* Clear to Send */
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#define UART8250_MSR_DDCD 0x08 /* Delta DCD */
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#define UART8250_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART8250_MSR_DDSR 0x02 /* Delta DSR */
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#define UART8250_MSR_DCTS 0x01 /* Delta CTS */
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#define UART8250_SCR 0x07
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#define UART8250_SPR 0x07
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#if CONFIG_CONSOLE_SERIAL
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#if ((115200 % CONFIG_TTYS0_BAUD) != 0)
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#error Bad ttyS0 baud rate
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#endif
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#endif
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/* Line Control Settings */
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#define UART8250_LCS CONFIG_TTYS0_LCS
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#if CONFIG_CONSOLE_SERIAL8250
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unsigned char uart8250_rx_byte(unsigned base_port);
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int uart8250_can_rx_byte(unsigned base_port);
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void uart8250_tx_byte(unsigned base_port, unsigned char data);
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void uart8250_tx_flush(unsigned base_port);
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/* Yes it is silly to have three different uart init functions. But we used to
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* have three different sets of uart code, so it's an improvement.
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*/
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void uart8250_init(unsigned base_port, unsigned divisor);
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void uart_init(void);
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#endif
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#if CONFIG_CONSOLE_SERIAL8250MEM
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void uartmem_init(void);
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/* and the same for memory mapped uarts */
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unsigned char uart8250_mem_rx_byte(unsigned base_port);
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int uart8250_mem_can_rx_byte(unsigned base_port);
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void uart8250_mem_tx_byte(unsigned base_port, unsigned char data);
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void uart8250_mem_tx_flush(unsigned base_port);
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void uart8250_mem_init(unsigned base_port, unsigned divisor);
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u32 uart_mem_init(void);
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#if defined(__PRE_RAM__) && CONFIG_DRIVERS_OXFORD_OXPCIE
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/* and special init for OXPCIe based cards */
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extern int oxford_oxpcie_present;
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void oxford_init(void);
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#endif
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#endif
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#endif /* __UART8250_H__ */
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