Timothy Pearson 4cde9784e0 southbridge/amd/sr5650: Fix GPP3a link training in higher width modes ... Change-Id: I7503ae42eb8bc91411413ef2cc7e7a723df7091a Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11990 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)		2015-10-23 20:02:52 +02:00
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acpi
arch	armv7: Word-sized/half-word-sized memory operations for 32/16 bit read/write	2015-10-17 18:10:29 +00:00
commonlib	vboot: prepare for x86 verstage	2015-10-11 23:57:29 +00:00
console	x86: add standalone verstage support	2015-10-14 17:07:52 +00:00
cpu	cpu/amd/model_10xxx: Clean up debugging statements	2015-10-23 19:59:40 +02:00
device	device/hypertransport: Add additional debug output	2015-10-23 20:00:07 +02:00
drivers	gma ACPI: Make brightness levels a per board setting	2015-10-22 23:01:36 +02:00
ec	ec/google: Move label to BOL to satisfy lint-tests	2015-10-15 07:36:26 +00:00
include	include/smbios: Update SMBIOS memory structures to version 2.8	2015-10-23 19:58:17 +02:00
lib	Revert "coreboot_table: don't add CMOS checksum twice."	2015-10-20 16:35:12 +02:00
mainboard	intel/cougar_canyon2: fix build	2015-10-23 11:38:53 +02:00
northbridge	northbridge/amd/amdmct/mct_ddr3: Fix curly brace style violations	2015-10-23 19:58:48 +02:00
soc	soc/intel/broadwell: fix USBDEBUG copy-pasta	2015-10-15 17:48:17 +00:00
southbridge	southbridge/amd/sr5650: Fix GPP3a link training in higher width modes	2015-10-23 20:02:52 +02:00
superio
vendorcode	Revert "Remove sandybridge and ivybridge FSP code path"	2015-10-22 21:51:01 +02:00
Kconfig	Enable MULTIPLE_CBFS_INSTANCES on x86, too	2015-10-20 16:39:00 +02:00