Felix Held 4cd9ac0a55 soc/amd/picasso/mca: don't do out of bounds array accesses ... The Picasso APUs advertise 23 MCA banks in the lower byte of the IA32_MCG_CAP MSR, which is more than the 7 core MCA banks. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>		2021-03-14 15:08:09 +00:00
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cezanne	soc/amd/cezanne/acpi/soc.asl: Include sleepstates.asl	2021-03-13 23:15:15 +00:00
common	soc/amd/common/block/graphics/graphics: GOP: load VBIOS	2021-03-13 02:44:40 +00:00
picasso	soc/amd/picasso/mca: don't do out of bounds array accesses	2021-03-14 15:08:09 +00:00
stoneyridge	soc/amd: move warm reset flag function prototypes to common code	2021-03-11 15:11:20 +00:00
Kconfig	soc/amd: rename common Kconfig and use wildcard for SoC-specific Kconfig	2020-11-19 14:29:14 +00:00