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coreboot/src/cpu/intel
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Stefan Reinauer 4cc8c70c32 Rework ACPI CST table generation 
... in order to unify the Sandybridge and Lenovo implementations
currently used in the tree.

- use acpi_addr_t in acpigen_write_register()
- use acpi_cstate_t for cstate tables (and fix up
  the x60 and t60)
- drop cst_entry from acpigen.h

Change-Id: Icb87418d44d355f607c4a67300107b40f40b3b3f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/943
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2012-04-30 23:05:40 +02:00
..
car Replace cache control magic numbers with symbols 2012-04-25 16:27:07 +02:00
ep80579 MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
hyperthreading Intel cpus: Fix deadlock on hyper-threading init 2012-03-25 20:33:28 +02:00
microcode microcode: print date of microcode and unify output 2012-04-26 02:32:04 +02:00
model_6bx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6dx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_6ex Replace cache control magic numbers with symbols 2012-04-25 16:27:07 +02:00
model_6fx Replace cache control magic numbers with symbols 2012-04-25 16:27:07 +02:00
model_6xx MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_65x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_67x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_68x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_69x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_106cx Replace cache control magic numbers with symbols 2012-04-25 16:27:07 +02:00
model_206ax Revamp Intel microcode update code 2012-04-26 00:46:35 +02:00
model_1067x Intel cpus: apply un-written naming rules 2012-02-10 23:40:07 +01:00
model_f0x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f1x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f2x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f3x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
model_f4x MTRR: get physical address size from CPUID 2012-01-10 21:51:40 +01:00
slot_1 cpu/intel/slot_1: Init L2 cache on SECC(2) CPUs. 2011-08-04 08:10:12 +02:00
slot_2 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
socket_441 oops. this is weird. CAR addresses should be specified in the socket and not in 2011-01-27 01:11:20 +00:00
socket_BGA956 Intel cpus: apply un-written naming rules 2012-02-10 23:40:07 +01:00
socket_FC_PGA370 Get rid of the old romstage-as-bootblock ROM layout 2011-10-28 22:17:36 +02:00
socket_LGA771 Intel cpus: Include CAR from socket 2012-03-17 09:38:31 +01:00
socket_mFCBGA479 Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mFCPGA478 Intel cpus: Include CAR from socket 2012-03-17 09:38:31 +01:00
socket_mPGA478 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA479M Move "select CACHE_AS_RAM" lines from boards into CPU socket. 2010-12-08 08:22:04 +00:00
socket_mPGA603 Rename build system variables to be more intuitive, and 2010-09-30 16:55:02 +00:00
socket_mPGA604 Fix support for RAM-less multi-processor init 2012-04-06 04:57:04 +02:00
socket_PGA370 Drop unused DCACHE_RAM_BASE from intel/car/cache_as_ram.inc-using sockets. 2010-10-15 07:47:51 +00:00
socket_rPGA989 Add support for Intel Sandybridge CPU 2012-04-05 21:10:25 +02:00
speedstep Rework ACPI CST table generation 2012-04-30 23:05:40 +02:00
thermal_monitoring drop unused code (trivial) 2008-08-01 11:53:39 +00:00
turbo Add support for Intel Turbo Boost feature 2012-04-03 20:29:33 +02:00
Kconfig Add support for Intel Sandybridge CPU 2012-04-05 21:10:25 +02:00
Makefile.inc Add support for Intel Sandybridge CPU 2012-04-05 21:10:25 +02:00