coreboot/src/soc
Hsiao Chien Sung 4c0dc4ee91 soc/mediatek/mt8188: Support 4K resolution display
The original clock rate 416MHz is insufficient for 4K resolution and
causing the screen to glitch. Set the clock rate to 594MHz to support
4K resolution.

BUG=b:236328487
TEST=Glitching screen was fixed after applying this patch

Change-Id: Ic40dd28264d03ef7218ff4edd8d4182e0fe74ea3
Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com>
Signed-off-by: Jason Chen <Jason-ch.Chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75661
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-12 15:31:53 +00:00
..
amd soc/amd/smm: Sanity check the SMM TSEG size 2023-06-12 15:28:09 +00:00
cavium soc/cavium/cn81xx: Use correct size for MPIDR_EL1 register 2023-05-13 17:22:16 +00:00
example/min86
intel soc/intel/common: Make get_ramtop_addr non static 2023-06-07 22:00:47 +00:00
mediatek soc/mediatek/mt8188: Support 4K resolution display 2023-06-12 15:31:53 +00:00
nvidia treewide: stop calling custom TPM log "TCPA" 2023-01-11 16:00:55 +00:00
qualcomm treewide: Remove 'extern' from functions declaration 2023-05-26 13:45:24 +00:00
rockchip cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00
samsung treewide: Fix old-style declarations 2023-01-17 04:23:49 +00:00
sifive/fu540 soc/sifive: Comment out set but unused variables 2023-06-04 19:22:50 +00:00
ti src/soc/ti: Remove unnecessary space after casts 2022-11-22 13:42:28 +00:00
ucb/riscv cbmem_top_chipset: Change the return value to uintptr_t 2022-11-18 16:00:45 +00:00