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4be8900ca3
This patch changes the ram_media CBFS backend implementation to no longer detect an absolute address that is inside the "memory region" used to back the CBFS image (which on x86 is really just the memory-mapped flash due to a depthcharge implementation detail). This was (as far as I know only) used to support the ugly CBFS header pointer situation with SeaBIOS, which is now resolved. It is a very dangerous feature, since it's perfectly possible for a negative offset relative to the end of the image to overlap that region. We only get lucky that in our existing use cases the embedded CBFS is further away from the end of the ROM than it's own size... if we instead had a 3MB image from 0xfffd0000 to 0xffff0000, then we might want to pass in an address like 0xfffe8000 (interpreted as a relative offset from the end) to refer to the absolute address 0xfffd8000, but this feature would prevent that since it fits inside the window when interpreted absolutely. (Also, it is unlikely but possible that a non-memory-mapped architecture which starts DRAM at 0x0 may put its bounce buffer within the first few megabyte of the address space, so that a relative offset from the start of the image could be interpreted as an absolute offset inside the buffer. CQ-DEPEND=CL:229962 BRANCH=None BUG=None TEST=Built and booted on Falco and Nyan_Blaze, confirmed that legacy mode still works as well as before. Change-Id: I0c9149d725adeecef2520342b307ce7ea52990c1 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/229976 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org> |
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------------------------------------------------------------------------------- coreboot README ------------------------------------------------------------------------------- coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload. With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required. coreboot was formerly known as LinuxBIOS. Payloads -------- After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot. See http://www.coreboot.org/Payloads for a list of supported payloads. Supported Hardware ------------------ coreboot supports a wide range of chipsets, devices, and mainboards. For details please consult: * http://www.coreboot.org/Supported_Motherboards * http://www.coreboot.org/Supported_Chipsets_and_Devices Build Requirements ------------------ * gcc / g++ * make Optional: * doxygen (for generating/viewing documentation) * iasl (for targets with ACPI support) * gdb (for better debugging facilities on some targets) * ncurses (for 'make menuconfig') * flex and bison (for regenerating parsers) Building coreboot ----------------- Please consult http://www.coreboot.org/Build_HOWTO for details. Testing coreboot Without Modifying Your Hardware ------------------------------------------------ If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU. Please see http://www.coreboot.org/QEMU for details. Website and Mailing List ------------------------ Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website: http://www.coreboot.org You can contact us directly on the coreboot mailing list: http://www.coreboot.org/Mailinglist Copyright and License --------------------- The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details. coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details. This makes the resulting coreboot images licensed under the GPL, version 2.