coreboot/src/soc
Michael Niewöhner 38107fa80e acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table
Some elements in the ACPI CPPC table allow static DWORDs. Instead of
using a fake register resource, use a tagged union with the two types
"register" and "DWORD" and respective macros for CPPC table entries.

Test: dumped SSDT before and after do not differ.

Change-Id: Ib853261b5c0ea87ae2424fed188f2d1872be9a06
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-10-21 20:03:14 +00:00
..
amd acpigen,soc/amd,cpu/intel: rework static DWORD for CPPC table 2021-10-21 20:03:14 +00:00
cavium src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
example
intel soc/intel/alderlake: Fix wrong FIVR configs assignment 2021-10-20 15:48:38 +00:00
mediatek soc/mediatek/mt8192: add tracker dump 2021-10-13 13:58:01 +00:00
nvidia src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
qualcomm sc7280: Add GSI FW download support 2021-10-18 18:28:53 +00:00
rockchip
samsung src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
sifive src/soc to src/superio: Fix spelling errors 2021-10-05 18:07:08 +00:00
ti
ucb