Jonathon Hall 4dfa90613c soc/intel/cannonlake: Support Comet Lake v1 and v2 in one build ... Define SOC_INTEL_COMETLAKE_1_2, which creates a build supporting both Comet Lake v1 and v2 by including both sets of FSP binaries and selecting one based on the CPUID. A mainboard can select this instead of SOC_INTEL_COMETLAKE_1 or ..._2 to support all CML-U steppings in one build. Change-Id: Ic8bf444560fd6b57064c47faf038643fabde010e Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78345 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>		2023-10-20 14:20:08 +00:00
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amd	soc/amd/common/data_fabric_helper: add pre-processor guards for ACPI	2023-10-16 14:20:35 +00:00
cavium	Kconfig: Bring HEAP_SIZE to a common, large value	2023-10-11 12:09:01 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel/cannonlake: Support Comet Lake v1 and v2 in one build	2023-10-20 14:20:08 +00:00
mediatek	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
nvidia	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
qualcomm	Kconfig: Bring HEAP_SIZE to a common, large value	2023-10-11 12:09:01 +00:00
rockchip	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
samsung	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
sifive/fu540	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
ti	src/soc/ti: Remove unnecessary space after casts	2022-11-22 13:42:28 +00:00
ucb/riscv	cbmem_top_chipset: Change the return value to uintptr_t	2022-11-18 16:00:45 +00:00