Raul E Rangel 43aa527eec soc/amd/common/block/espi: Explicitly assert PLTRST# ... PLTRST# is currently asserted and latched when eSPI_RST# gets asserted. If eSPI_RST# isn't used on a platform or it doesn't properly assert in all cases, then PLTRST# will never be asserted. This could result in the AP and EC being out of sync. BUG=b:188188172, b:188935533 TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral channel is correctly reset. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>		2021-05-30 20:28:41 +00:00
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acpi	soc/amd/picasso/acpi/cpu: move WAL1 method that calls ALIB to common	2021-05-08 18:21:25 +00:00
block	soc/amd/common/block/espi: Explicitly assert PLTRST#	2021-05-30 20:28:41 +00:00
fsp	soc/amd/common/fsp/pci: Add helper methods for PCI IRQ table	2021-05-09 18:09:36 +00:00
psp_verstage	soc/amd/picasso: fix MCACHE on psp_verstage RO boot	2021-05-28 16:16:28 +00:00
vboot	amd/vboot: remove bl_syscall_public.h from include	2021-04-23 16:33:44 +00:00
Kconfig.common	soc/amd/common: Add Kconfig/Makefile support for common/fsp/*	2021-05-07 18:43:41 +00:00
Makefile.inc	soc/amd/picasso: move chipset_handle_reset to common	2020-12-11 17:44:19 +00:00