coreboot/src/soc/intel
Aaron Durbin 439356fabc x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.

Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-04 15:09:32 +00:00
..
baytrail x86: remove cpu_incs as romstage Make variable 2015-09-04 15:09:32 +00:00
braswell soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM 2015-08-31 15:38:05 +00:00
broadwell x86: remove cpu_incs as romstage Make variable 2015-09-04 15:09:32 +00:00
common fsp raminit: Add romstage_params to soc_memory_init_params 2015-08-29 07:11:34 +00:00
fsp_baytrail intel/fsp_baytrail: Support Baytrail FSP Gold4 release 2015-07-21 22:32:23 +02:00
skylake soc/intel: Fix dependency of CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM 2015-08-31 15:38:05 +00:00