coreboot/src/cpu/intel/haswell
Aaron Durbin 439356fabc x86: remove cpu_incs as romstage Make variable
When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.

BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.

Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-04 15:09:32 +00:00
..
acpi Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
acpi.c device_ops: add device_t argument to acpi_fill_ssdt_generator 2015-06-05 21:11:43 +02:00
bootblock.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
cache_as_ram.inc Intel: Remove CACHE_MRC_BIN - 'selected' everywhere in Kconfig 2015-08-25 17:36:45 +00:00
chip.h intel: Remove pstate_coord_type. 2015-05-28 11:19:21 +02:00
finalize.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
haswell.h Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
haswell_init.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
Kconfig smm: Merge configs SMM_MODULES and SMM_TSEG 2015-05-28 22:07:58 +02:00
Makefile.inc x86: remove cpu_incs as romstage Make variable 2015-09-04 15:09:32 +00:00
microcode_blob.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
monotonic_timer.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
romstage.c stage_cache: use cbmem init hooks 2015-06-09 22:06:40 +02:00
smmrelocate.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00
stage_cache.c haswell: Link stage_cache_external_region into ramstage, too 2015-05-05 03:39:41 +02:00
tsc_freq.c Remove address from GPLv2 headers 2015-05-21 20:50:25 +02:00