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Tim Wawrzynczak 43607e4751 soc/intel/alderlake: Enable support for common IRQ block 
Since GPIO IO-APIC IRQs are fixed in hardware (RO registers), this patch
allows ADL boards to dynamically assign PCI IRQs. This means not relying
on FSP defaults, which eliminates the problem of PCI IRQs interfering
with GPIO IRQs routed to the same IRQ, when both have selected IO-APIC
routing.

BUG=b:176858827
TEST=brya0, grep 'IO-APIC' /proc/interrupts (compressed to fit)
   0:   36     0  0  0     0    0    0   0   IO-APIC    2-edge      time
   1:    0     0  9  0     0    0    0   0   IO-APIC    1-edge      i804
   8:    0     0  0  0     0    0    0   0   IO-APIC    8-edge      rtc0
   9:    0 21705  0  0     0    0    0   0   IO-APIC    9-fasteoi   acpi
  14:    0     0  0  0     0    0    0   0   IO-APIC   14-fasteoi   INTC
  18:    0     0  0  0     0    0    0   0   IO-APIC   18-fasteoi   inte
  20:    0     0  0  0     0    0    0 394   IO-APIC   20-fasteoi   idma
  23: 2280     0  0  0     0    0    0   0   IO-APIC   23-fasteoi   idma
  26:    0     0 26  0     0    0    0   0   IO-APIC   26-fasteoi   idma
  27:    0     0  0  6     0    0    0   0   IO-APIC   27-fasteoi   idma
  28:    0     0  0  0     0    0    0   0   IO-APIC   28-fasteoi   idma
  29:    0     0  0  0 25784    0    0   0   IO-APIC   29-fasteoi   idma
  30:    0     0  0  0     0    0    0   0   IO-APIC   30-fasteoi   idma
  31:    0     0  0  0     0    0  226   0   IO-APIC   31-fasteoi   idma
  77:    0     0  0  0     0 2604    0   0   IO-APIC   77-edge      cr50
 100:    0     0  0  0     0    0    0   0   IO-APIC  100-fasteoi   ELAN
 103:    0     0  0  0     0    0    0   0   IO-APIC  103-fasteoi   chro
abbreviated _PRT dump:
    If (PICM)
          Package (){0x0002FFFF, 0, 0, 0x10},
          Package (){0x0004FFFF, 0, 0, 0x11},
          Package (){0x0005FFFF, 0, 0, 0x12},
          Package (){0x0006FFFF, 0, 0, 0x13},
          Package (){0x0006FFFF, 1, 0, 0x14},
          Package (){0x0007FFFF, 0, 0, 0x15},
          Package (){0x0007FFFF, 1, 0, 0x16},
          Package (){0x0007FFFF, 2, 0, 0x17},
          Package (){0x0007FFFF, 3, 0, 0x10},
          Package (){0x000DFFFF, 0, 0, 0x11},
          Package (){0x0012FFFF, 0, 0, 0x18},
          Package (){0x0012FFFF, 1, 0, 0x19},
          Package (){0x0014FFFF, 0, 0, 0x12},
          Package (){0x0014FFFF, 1, 0, 0x13},
          Package (){0x0015FFFF, 0, 0, 0x1A},
          Package (){0x0015FFFF, 1, 0, 0x1B},
          Package (){0x0015FFFF, 2, 0, 0x1C},
          Package (){0x0015FFFF, 3, 0, 0x1D},
          Package (){0x0016FFFF, 0, 0, 0x14},
          Package (){0x0016FFFF, 1, 0, 0x15},
          Package (){0x0016FFFF, 2, 0, 0x16},
          Package (){0x0016FFFF, 3, 0, 0x17},
          Package (){0x0017FFFF, 0, 0, 0x10},
          Package (){0x0019FFFF, 0, 0, 0x1E},
          Package (){0x0019FFFF, 1, 0, 0x1F},
          Package (){0x0019FFFF, 2, 0, 0x20},
          Package (){0x001CFFFF, 0, 0, 0x10},
          Package (){0x001CFFFF, 1, 0, 0x11},
          Package (){0x001CFFFF, 2, 0, 0x12},
          Package (){0x001CFFFF, 3, 0, 0x13},
          Package (){0x001DFFFF, 0, 0, 0x10},
          Package (){0x001DFFFF, 1, 0, 0x11},
          Package (){0x001DFFFF, 2, 0, 0x12},
          Package (){0x001DFFFF, 3, 0, 0x13},
          Package (){0x001EFFFF, 0, 0, 0x14},
          Package (){0x001EFFFF, 1, 0, 0x15},
          Package (){0x001EFFFF, 2, 0, 0x16},
          Package (){0x001EFFFF, 3, 0, 0x17},
          Package (){0x001FFFFF, 1, 0, 0x15},
          Package (){0x001FFFFF, 2, 0, 0x16},
          Package (){0x001FFFFF, 3, 0, 0x17},
          Package (){0x001FFFFF, 0, 0, 0x14},
    Else
          Package (){0x0002FFFF, 0, 0, 0x0B},
	  Package (){0x0004FFFF, 0, 0, 0x0A},
	  Package (){0x0005FFFF, 0, 0, 0x0B},
	  Package (){0x0006FFFF, 0, 0, 0x0B},
	  Package (){0x0006FFFF, 1, 0, 0x0B},
	  Package (){0x0007FFFF, 0, 0, 0x0B},
	  Package (){0x0007FFFF, 1, 0, 0x0B},
	  Package (){0x0007FFFF, 2, 0, 0x0B},
	  Package (){0x0007FFFF, 3, 0, 0x0B},
	  Package (){0x000DFFFF, 0, 0, 0x0A},
	  Package (){0x0014FFFF, 0, 0, 0x0B},
	  Package (){0x0014FFFF, 1, 0, 0x0B},
	  Package (){0x0016FFFF, 0, 0, 0x0B},
	  Package (){0x0016FFFF, 1, 0, 0x0B},
	  Package (){0x0016FFFF, 2, 0, 0x0B},
	  Package (){0x0016FFFF, 3, 0, 0x0B},
	  Package (){0x0017FFFF, 0, 0, 0x0B},
	  Package (){0x001CFFFF, 0, 0, 0x0B},
	  Package (){0x001CFFFF, 1, 0, 0x0A},
	  Package (){0x001CFFFF, 2, 0, 0x0B},
	  Package (){0x001CFFFF, 3, 0, 0x0B},
	  Package (){0x001DFFFF, 0, 0, 0x0B},
	  Package (){0x001DFFFF, 1, 0, 0x0A},
	  Package (){0x001DFFFF, 2, 0, 0x0B},
	  Package (){0x001DFFFF, 3, 0, 0x0B},
	  Package (){0x001EFFFF, 0, 0, 0x0B},
	  Package (){0x001EFFFF, 1, 0, 0x0B},
	  Package (){0x001EFFFF, 2, 0, 0x0B},
	  Package (){0x001EFFFF, 3, 0, 0x0B},
	  Package (){0x001FFFFF, 1, 0, 0x0B},
	  Package (){0x001FFFFF, 2, 0, 0x0B},
	  Package (){0x001FFFFF, 3, 0, 0x0B},
	  Package (){0x001FFFFF, 0, 0, 0x0B},
dmesg shows no GSI or PCI errors, TPM & touchpad IRQs still work

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1e7a708183ac4170b28da9565137fa2f5088a7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-06-29 21:54:00 +00:00
3rdparty security/intel/cbnt: Build test CBnT provisioning 2021-06-28 04:13:54 +00:00
configs security/intel/cbnt: Build test CBnT provisioning 2021-06-28 04:13:54 +00:00
Documentation mb/google/trogdor: Add new vaviant mrbland 2021-06-24 21:06:20 +00:00
LICENSES treewide: Remove trailing whitespace 2021-02-17 17:30:05 +00:00
payloads nvs: Add Chrome OS NVS (CNVS) information to coreboot tables 2021-06-18 18:38:14 +00:00
src soc/intel/alderlake: Enable support for common IRQ block 2021-06-29 21:54:00 +00:00
tests helpers: Introduce retry macro 2021-06-26 10:09:06 +00:00
util security/intel/cbnt: Build test CBnT provisioning 2021-06-28 04:13:54 +00:00
.checkpatch.conf lint: checkpatch: Only exclude specific src/vendorcode/ subdirectories 2021-04-06 16:04:41 +00:00
.clang-format lint/clang-format: set to 96 chars per line 2019-06-13 20:14:00 +00:00
.editorconfig Add .editorconfig file 2019-09-10 12:52:18 +00:00
.gitignore .gitignore: Ignore .test/.dependencies globally 2020-10-31 18:21:36 +00:00
.gitmodules .gitmodules: Update intel-microcode submodule to track branch=main 2021-06-09 17:20:50 +00:00
.gitreview add .gitreview 2012-11-01 23:13:39 +01:00
AUTHORS AUTHORS, util/: Drop individual copyright notices 2020-05-09 21:21:32 +00:00
COPYING update license template. 2006-08-12 22:03:36 +00:00
gnat.adc treewide: Remove "this file is part of" lines 2020-05-11 17:11:40 +00:00
MAINTAINERS Revert "src/mainboard: Add Star Labs labtop series" 2021-06-04 18:52:32 +00:00
Makefile tests: improve code coverage support 2021-05-19 19:56:02 +00:00
Makefile.inc option: Introduce CMOS_LAYOUT_FILE Kconfig symbol 2021-05-18 11:43:49 +00:00
README.md README.md: Remove link to deprecated wiki 2019-11-16 20:39:55 +00:00
toolchain.inc toolchain.inc: Update and fix the test-toolchain target 2021-02-24 11:29:39 +00:00

README.md

coreboot README

coreboot is a Free Software project aimed at replacing the proprietary BIOS (firmware) found in most computers. coreboot performs a little bit of hardware initialization and then executes additional boot logic, called a payload.

With the separation of hardware initialization and later boot logic, coreboot can scale from specialized applications that run directly firmware, run operating systems in flash, load custom bootloaders, or implement firmware standards, like PC BIOS services or UEFI. This allows for systems to only include the features necessary in the target application, reducing the amount of code and flash space required.

coreboot was formerly known as LinuxBIOS.

Payloads

After the basic initialization of the hardware has been performed, any desired "payload" can be started by coreboot.

See https://www.coreboot.org/Payloads for a list of supported payloads.

Supported Hardware

coreboot supports a wide range of chipsets, devices, and mainboards.

For details please consult:

Build Requirements

  • make
  • gcc / g++ Because Linux distribution compilers tend to use lots of patches. coreboot does lots of "unusual" things in its build system, some of which break due to those patches, sometimes by gcc aborting, sometimes - and that's worse - by generating broken object code. Two options: use our toolchain (eg. make crosstools-i386) or enable the ANY_TOOLCHAIN Kconfig option if you're feeling lucky (no support in this case).
  • iasl (for targets with ACPI support)
  • pkg-config
  • libssl-dev (openssl)

Optional:

  • doxygen (for generating/viewing documentation)
  • gdb (for better debugging facilities on some targets)
  • ncurses (for make menuconfig and make nconfig)
  • flex and bison (for regenerating parsers)

Building coreboot

Please consult https://www.coreboot.org/Build_HOWTO for details.

Testing coreboot Without Modifying Your Hardware

If you want to test coreboot without any risks before you really decide to use it on your hardware, you can use the QEMU system emulator to run coreboot virtually in QEMU.

Please see https://www.coreboot.org/QEMU for details.

Website and Mailing List

Further details on the project, a FAQ, many HOWTOs, news, development guidelines and more can be found on the coreboot website:

https://www.coreboot.org

You can contact us directly on the coreboot mailing list:

https://www.coreboot.org/Mailinglist

Copyright and License

The copyright on coreboot is owned by quite a large number of individual developers and companies. Please check the individual source files for details.

coreboot is licensed under the terms of the GNU General Public License (GPL). Some files are licensed under the "GPL (version 2, or any later version)", and some files are licensed under the "GPL, version 2". For some parts, which were derived from other projects, other (GPL-compatible) licenses may apply. Please check the individual source files for details.

This makes the resulting coreboot images licensed under the GPL, version 2.