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multiple links. The way this was done in v2 was a big confusing; this way is
less so.
The changes are easy. Getting them right has been hard :-)
First, for a k8 north that has three links, you can name each one as follows:
pci0@18,0
pci1@18,0
pci2@18,0
We have to have the same pcidevfn on these because that is how the k8 works.
But the unit numbers (pci0, pci1, etc.) distinguish them.
The dts will properly generate a "v3 device code"
compatible static tree that puts the links in the right place in the
data structure.
The changes to dts are trivial.
As before, dts nodes with children are understood to be a bridge.
But what if there is a dts entry like this:
pci1@18,0 {/config/("northbridge/amd/k8/pci");};
This entry has no children in the dts.
How does dt compiler know it is a bridge? It can not know unless
we add information to the dts for that northbridge part.
To ensure that all bridge devices are detected, we support the following:
if a dts node for a device has a bridge property, e.g.:
{
device_operations = "k8_ops";
bridge;
};
The dt compiler will treat it as a bridge whether it has children or not.
Why would a device not have children? Because it might be attached to a
pci or other socket, and we don't know at build time if the socket is empty,
or what might be in the socket.
This code has been tested on dbe62 and k8 simnow, and works on each.
It is minimal in size and it does what we need. I hope it resolves our
discussion for now. We might want to improve or change the device code
later but, at this point, forward motion is important -- I'm on a deadline for
a very important demo Oct. 22!
Also included in this patch are new debug prints in k8 north.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://coreboot.org/repository/coreboot-v3@865 f3766cd6-281f-0410-b1cd-43a5c92072e9
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118 lines
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2006 Segher Boessenkool <segher@kernel.crashing.org>
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## Copyright (C) 2006-2007 coresystems GmbH
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## (Written by Stefan Reinauer <stepan@coresystems.de> for coresystems GmbH)
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## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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menu "Mainboard"
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choice
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prompt "Mainboard vendor"
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default VENDOR_EMULATION
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config VENDOR_ADL
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bool "Advanced Digital Logic"
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help
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Select this option for various systems from Advanced Digital Logic.
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config VENDOR_AMD
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bool "AMD"
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help
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Select this option for various systems from
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Advanced Micro Devices, Inc.
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config VENDOR_AMP
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bool "AMP"
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help
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Select this option for various systems from
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Advanced Micro Devices, Inc.
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config VENDOR_ARTECGROUP
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bool "Artec Group"
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help
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Select this option for various systems from the Artec Group.
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config VENDOR_GIGABYTE
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bool "Gigabyte"
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help
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Select this option for various systems from Gigabyte
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config VENDOR_EMULATION
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bool "Emulated systems"
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help
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Select this option for various system emulators, such as QEMU.
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config VENDOR_PCENGINES
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bool "PC Engines"
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help
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Select this option for PC Engines systems.
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endchoice
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source "mainboard/adl/Kconfig"
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source "mainboard/amd/Kconfig"
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source "mainboard/amp/Kconfig"
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source "mainboard/artecgroup/Kconfig"
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source "mainboard/emulation/Kconfig"
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source "mainboard/gigabyte/Kconfig"
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source "mainboard/pcengines/Kconfig"
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choice
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prompt "ROM chip size"
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default COREBOOT_ROMSIZE_KB_256
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config COREBOOT_ROMSIZE_KB_128
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bool "128 KB"
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help
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Choose this option if you have a 128 KB ROM chip.
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config COREBOOT_ROMSIZE_KB_256
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bool "256 KB"
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help
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Choose this option if you have a 256 KB ROM chip.
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config COREBOOT_ROMSIZE_KB_512
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bool "512 KB"
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help
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Choose this option if you have a 512 KB ROM chip.
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config COREBOOT_ROMSIZE_KB_1024
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bool "1024 KB (1 MB)"
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help
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Choose this option if you have a 1024 KB (1 MB) ROM chip.
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config COREBOOT_ROMSIZE_KB_2048
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bool "2048 KB (2 MB)"
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help
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Choose this option if you have a 2048 KB (2 MB) ROM chip.
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endchoice
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config COREBOOT_ROMSIZE_KB
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int
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default 128 if COREBOOT_ROMSIZE_KB_128
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default 256 if COREBOOT_ROMSIZE_KB_256
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default 512 if COREBOOT_ROMSIZE_KB_512
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default 1024 if COREBOOT_ROMSIZE_KB_1024
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default 2048 if COREBOOT_ROMSIZE_KB_2048
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help
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Map the config names to an integer.
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endmenu
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