Felix Held 42d5294793 vc/amd/fsp/picasso: document DXIO lane number mapping ... Haven't found the official documentation for the DXIO lane mapping on Pollock, so I had to guess that from the working configurations used in google/dalboz and amd/cereme. Change-Id: I53aac0aeba8466ae456f0f935114b587b64eeeaa Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44063 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-07-31 21:05:34 +00:00
..
acpi	src/acpi: Add missing <{stdbool,stdint}.h>	2020-07-29 09:37:10 +00:00
arch	mb/ocp/deltalake: Update SMBIOS type 4 -- Processor Information	2020-07-31 09:30:47 +00:00
commonlib
console
cpu	cpu/intel/car/romstage.c: Remove unused <bootblock_common.h>	2020-07-26 21:38:22 +00:00
device	device: Add find_dev_nested_path helper function	2020-07-28 19:28:22 +00:00
drivers	drivers/ipmi/ocp: Add function to support OCP specific ipmi command	2020-07-31 09:31:16 +00:00
ec	ec/lenovo/h8: Align macro values in one column	2020-07-26 21:40:00 +00:00
include	mb/ocp/deltalake: Update SMBIOS type 4 -- Processor Information	2020-07-31 09:30:47 +00:00
lib	lib/ubsan.c: Update error handlers for current toolchain's GCC	2020-07-31 19:53:27 +00:00
mainboard	mb/ocp/deltalake: configure DIMM_MAX	2020-07-31 09:33:33 +00:00
northbridge	nb/intel/x4x/rcven.c: Rename memory barrier function	2020-07-30 22:50:12 +00:00
security	security/intel/txt: Add Intel TXT support	2020-07-31 16:02:54 +00:00
soc	soc/intel/cannonlake: Fix DMAR when no iGPU is present	2020-07-31 09:42:16 +00:00
southbridge	src: Never set ISA Enable on PCI bridges	2020-07-28 10:54:02 +00:00
superio
vendorcode	vc/amd/fsp/picasso: document DXIO lane number mapping	2020-07-31 21:05:34 +00:00
Kconfig