coreboot/src
Caesar Wang 01cbe3b75a google/gru: change the sd power sequence
In the safety considerations, we should make sure the slot of SD is
enabled first, since we want to the power switch of corresponding is
powered up.

The different boards have the different power switch for sdmmc.
Some power switch IC need turn on delay for long time.

let's move the slot power of SD to romstage and avoid explicit delays
or per-board.

BRANCH=none
BUG=b:35813418, b:35573103
TEST=check the signal for children of gru, and boot up from sd card.

Change-Id: Id164e4c4c900c6b1ca0251fc27db4cd36c56f6ff
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea1b01cc13
Original-Change-Id: I48ab543143d3de9be46608fc12d78e09decf8d79
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/447076
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19430
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
2017-04-25 10:51:28 +02:00
..
acpi
arch arch/x86: Add read64 and write64 functions 2017-04-25 06:14:39 +02:00
commonlib include: Add xmalloc, xzmalloc and dma routines 2017-04-25 00:52:03 +02:00
console console: Make snprintf available in all stages 2017-04-24 19:25:21 +02:00
cpu AGESA: Unify heap location 2017-04-15 11:16:10 +02:00
device libgfxinit: Select CONFIG_VGA when needed 2017-04-08 13:03:52 +02:00
drivers drivers/storage: Add SD/MMC/eMMC driver based upon depthcharge 2017-04-25 01:05:05 +02:00
ec ec/roda/it8518: Do EC write manually with long timeout 2017-04-08 13:17:56 +02:00
include drivers/storage: Add SD/MMC/eMMC driver based upon depthcharge 2017-04-25 01:05:05 +02:00
lib drivers/i2c/tpm: use iobuf library for marshaling commands 2017-04-24 19:07:07 +02:00
mainboard google/gru: change the sd power sequence 2017-04-25 10:51:28 +02:00
northbridge nb/intel/pineview: Select RELOCATABLE_RAMSTAGE 2017-04-24 19:47:10 +02:00
soc mediatek/mt8173: Add support for Dual DSI output 2017-04-25 02:36:55 +02:00
southbridge [nb|sb]/amd/[amdfam10|sb700]: Add LPC bridge ACPI names for NB/SB 2017-04-17 23:33:09 +02:00
superio superio/fintek: Add support for Fintek F71808A 2017-03-27 19:19:56 +02:00
vboot Remove libverstage as separate library and source file class 2017-03-28 22:18:53 +02:00
vendorcode Kconfig: provide MAINBOARD_HAS_TPM_CR50 option 2017-04-24 22:02:55 +02:00
Kconfig include: Add xmalloc, xzmalloc and dma routines 2017-04-25 00:52:03 +02:00