ffc1fb35aa
All but one board use the default value of enabled. Disabling this can only increase the number of MTRR registers used. Change-Id: I7d28adc31b9fae2301e4ff78fcb96486f81d5ec2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/1213 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
64 lines
1.4 KiB
Text
64 lines
1.4 KiB
Text
if ARCH_X86
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source src/cpu/amd/Kconfig
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source src/cpu/intel/Kconfig
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source src/cpu/via/Kconfig
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source src/cpu/x86/Kconfig
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config CACHE_AS_RAM
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bool
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default !ROMCC
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config DCACHE_RAM_BASE
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hex
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config DCACHE_RAM_SIZE
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hex
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config DCACHE_RAM_GLOBAL_VAR_SIZE
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hex
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default 0x0
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# FIXME MAX_PHYSICAL_CPUS should move to AMD specific code, or better
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# yet be dropped completely.
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config MAX_PHYSICAL_CPUS
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int
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default 1
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config SMP
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bool
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default y if MAX_CPUS != 1
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default n
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help
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This option is used to enable certain functions to make coreboot
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work correctly on symmetric multi processor (SMP) systems.
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config AP_SIPI_VECTOR
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hex
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default 0xfffff000
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help
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This must equal address of ap_sipi_vector from bootblock build.
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config MMX
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bool
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help
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Select MMX in your socket or model Kconfig if your CPU has MMX
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to MMX registers.
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config SSE
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bool
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help
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Select SSE in your socket or model Kconfig if your CPU has SSE
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streaming SIMD instructions. ROMCC can build more efficient
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code if it can spill to SSE (aka XMM) registers.
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config SSE2
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bool
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default n
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help
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Select SSE2 in your socket or model Kconfig if your CPU has SSE2
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streaming SIMD instructions. Some parts of coreboot can be built
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with more efficient code if SSE2 instructions are available.
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endif # ARCH_X86
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