Meera Ravindranath f3c42825f3 soc/intel/alderlake: Add CPU ID 0x906a4 ... TEST=Build and boot brya Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Change-Id: I4342c7343876eb40c2955f6f4dd99d6346852dc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/57610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>		2021-09-30 13:37:57 +00:00
..
cpu_ids.h	soc/intel/alderlake: Add CPU ID 0x906a4	2021-09-30 13:37:57 +00:00
em64t100_save_state.h
em64t101_save_state.h
fsb.h
hyperthreading.h
l2_cache.h
microcode.h	cpu/intel/microcode: Fix caching logic in intel_microcode_find	2021-03-12 17:33:01 +00:00
msr.h	soc/intel/car: Add support for bootguard CAR	2021-06-22 13:15:09 +00:00
smm_reloc.h
speedstep.h
turbo.h