Felix Held 41a5954a67 soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl ... To avoid code duplication and to also bring the mainboards using the Picasso SoC more in line with Cezanne and newer, factor out the SoC- specific code from the mainboard's dsdt.asl files to the SoC's soc.asl. TEST=Timeless builds result in identical images for Bilby, Mandolin, and Zork/Morphius Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id4ed3a3d3cb55c8b3b474c66a7c1700e24fe908e Reviewed-on: https://review.coreboot.org/c/coreboot/+/79653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>		2024-01-04 14:16:48 +00:00
..
amd	soc/amd/picasso/acpi: move SoC-common code from dsdt.asl to soc.asl	2024-01-04 14:16:48 +00:00
cavium	Revert "Kconfig: Bring HEAP_SIZE to a common, large value"	2023-11-07 17:35:39 +00:00
example/min86	soc: Remove SOC_SPECIFIC_OPTIONS	2023-08-21 23:45:43 +00:00
intel	soc/intel/meteorlake: Enable SSE2 accelerated RSA sign. verification	2024-01-02 03:40:18 +00:00
mediatek	soc/mediatek/mt8188: devapc: Allow APU to access BND_NORTH_APB2_S	2023-12-04 16:48:33 +00:00
nvidia	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
qualcomm	qualcomm/sc7180: Move QCSDI and increase romstage size by 4KB	2023-11-18 00:41:53 +00:00
rockchip	fmap: Map less space in fallback path without CBFS verification	2023-11-13 14:19:01 +00:00
samsung	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
sifive/fu540	memlayout.ld: Increase RAMSTAGE size to more than 1MB everywhere	2023-10-11 12:08:22 +00:00
ti
ucb/riscv