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coreboot/src/cpu/amd/agesa
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Stefan Reinauer 40f36e0d8d Make sure only one udelay function is available 
The Agesa wrapper and UDELAY_TIMER2 define their own timer functions,
so don't shove in UDELAY_IO

Change-Id: Ibe3345e825e0c074d5f531dba1198cd6e7b0a42d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-20 01:52:20 +01:00
..
family10 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
family12 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
family14 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
family15 Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
family15tn Remove chip.h files without config structure 2012-10-07 12:55:04 +02:00
apic_timer.c remove trailing whitespace 2011-11-01 19:07:45 +01:00
cache_as_ram.inc AMD agesa: add enable cache at the end of disable_cache_as_ram 2012-11-02 21:04:28 +01:00
Kconfig Make sure only one udelay function is available 2012-11-20 01:52:20 +01:00
Makefile.inc AGESA F15 wrapper for Trinity 2012-07-03 09:38:55 +02:00
s3_resume.c Make the device tree available in the rom stage 2012-08-04 18:05:39 +02:00
s3_resume.h AMD S3: Remove the hardcoded volatile position 2012-08-05 06:34:15 +02:00