Lijian Zhao 408d76f867 soc/intel/cannonlake: Add support for D0 stepping ... D0 stepping with CPUID 0x60663 need to be added in coreboot. TEST=Boot up with D0 stepping processor Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/22676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2017-12-11 19:29:15 +00:00
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acpi	arch/x86: Add common AMD ACPI hardware definitions	2017-11-10 19:15:38 +00:00
arch	arch/riscv: Remove supervisor_trap_entry	2017-12-02 05:25:16 +00:00
commonlib	commonlib: Add timestamp codes for AGESA	2017-12-11 17:31:38 +00:00
console	console: Ignore loglevel in nvram until ramstage	2017-09-25 13:35:29 +00:00
cpu	intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c	2017-12-11 01:10:51 +00:00
device	device/pciexp_device: Set values numerically instead of as bitmask	2017-12-08 11:38:05 +00:00
drivers	boardid: Minor clean up and standardization	2017-12-07 01:18:25 +00:00
ec	chromeec: Add command to override charger limit	2017-12-08 17:14:30 +00:00
include	intel: Use MSR_EBC_FREQUENCY_ID instead of 0x2c	2017-12-11 01:10:51 +00:00
lib	boardid: Add helpers to read sku_id strapping into coreboot tables	2017-12-07 01:19:32 +00:00
mainboard	google/gru: Stop mucking with unused I2S0 pins in codec config	2017-12-11 19:03:45 +00:00
northbridge	intel/i440bx: Correct RAM init programming	2017-12-09 16:54:44 +00:00
security	security/vboot: Remove unused include of vboot_nvstorage.h	2017-12-07 01:20:51 +00:00
soc	soc/intel/cannonlake: Add support for D0 stepping	2017-12-11 19:29:15 +00:00
southbridge	AMD fam10: Link southbridge/amd/rs780/early_setup.c	2017-12-11 11:58:02 +00:00
superio	winbond/w83977tf: Add ACPI declarations	2017-12-02 05:27:39 +00:00
vendorcode	vc/amd/pi/00670F00/binaryPI: cache the AGESA dispatcher	2017-12-11 01:07:31 +00:00
Kconfig	boardid: Switch from Kconfig to weak functions	2017-12-07 01:19:27 +00:00