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Rizwan Qureshi 4008890a69 UPSTREAM: kunimitsu: Add FSP 2.0 support in romstage 
Populate mainboard related Memory Init Params i.e, SPD
Rcomp values, DQ and DQs values.

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16316
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347
Reviewed-on: https://chromium-review.googlesource.com/380060
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15 13:41:25 -07:00
..
acpi
arch UPSTREAM: src/arch: Improve code formatting 2016-09-13 22:20:24 -07:00
commonlib UPSTREAM: commonlib: move DIV_ROUND macros from nvidia/tegra 2016-09-08 17:57:23 -07:00
console
cpu UPSTREAM: cpu/amd/family_10h-family_15h: transition away from device_t 2016-09-15 00:12:57 -07:00
device
drivers UPSTREAM: driver/intel/fsp2_0: Make FSP-M binary XIP 2016-09-15 13:41:21 -07:00
ec UPSTREAM: src/ec: Improve code formatting 2016-09-07 21:31:50 -07:00
include UPSTREAM: arch/arm: Add armv7-r configuration 2016-09-13 22:20:12 -07:00
lib UPSTREAM: edid: Fix a function signature 2016-09-09 12:33:33 -07:00
mainboard UPSTREAM: kunimitsu: Add FSP 2.0 support in romstage 2016-09-15 13:41:25 -07:00
northbridge UPSTREAM: i945.h: fix #include path 2016-09-15 00:12:59 -07:00
soc UPSTREAM: soc/intel/skylake: Add FSP 2.0 support in romstage 2016-09-15 13:41:23 -07:00
southbridge UPSTREAM: southbridge/amd/agesa/hudson: transition away from device_t 2016-09-15 00:12:52 -07:00
superio UPSTREAM: src/superio: Improve code formatting 2016-09-07 11:31:19 -07:00
vboot
vendorcode UPSTREAM: vendorcode/skylake: Add FSP header files without any adaptations 2016-09-13 22:20:08 -07:00
Kconfig UPSTREAM: Kconfig: Relocate DEVICETREE symbol 2016-09-07 21:31:34 -07:00