coreboot/src/northbridge/intel
Arthur Heymans 3f2f19d893 UPSTREAM: i945: Enable changing VRAM size
On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c

The intel documentation on i945, "Mobile Intel 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.

The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.

What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.

TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Reviewed-on: https://chromium-review.googlesource.com/380982
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-04 19:36:42 -07:00
..
common UPSTREAM: nb/intel: Factor out common MRC code 2016-06-13 15:55:25 -07:00
e7501 UPSTREAM: src/northbridge: Capitalize CPU, RAM and ROM 2016-08-04 23:37:04 -07:00
e7505 UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
fsp_rangeley header files: Fix guard name comments to match guard names 2016-01-18 04:07:53 +01:00
fsp_sandybridge northbridge/intel: move mrc_cache definition into a common header 2016-03-11 18:56:21 +01:00
gm45 UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
haswell UPSTREAM: src/northbridge: Capitalize CPU, RAM and ROM 2016-08-04 23:37:04 -07:00
i440bx northbridge/intel/i440bx: Unify UDELAY selection 2016-03-10 16:55:35 +01:00
i855 UPSTREAM: src/northbridge: Capitalize CPU, RAM and ROM 2016-08-04 23:37:04 -07:00
i945 UPSTREAM: i945: Enable changing VRAM size 2016-09-04 19:36:42 -07:00
i3100 UPSTREAM: src/northbridge: Capitalize CPU, RAM and ROM 2016-08-04 23:37:04 -07:00
i5000 tree: drop last paragraph of GPL copyright header 2015-10-31 21:37:39 +01:00
i82810 northbridge/intel/i82810: Unify UDELAY selection 2016-03-13 00:46:55 +01:00
i82830 UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
nehalem UPSTREAM: nb/intel/raminit (native): Read PCI mmio size from devicetree 2016-06-13 15:55:51 -07:00
pineview UPSTREAM: intel/pineview: Do not use scratchpad register for ACPI S3 2016-07-18 03:21:33 -07:00
sandybridge UPSTREAM: Remove non-ascii & unprintable characters 2016-08-05 11:45:20 -07:00
x4x UPSTREAM: x4x: make preallocated IGD memory a cmos option 2016-08-14 13:26:27 -07:00