Lee Leahy 3e5bc1feab soc/intel/common: Restrict common romstage/ramstage code to FSP ... Restrict the use of the common romstage/ramstage code to FSP 1.1 BRANCH=none BUG=None TEST=Build and run on cyan/sklrvp Change-Id: Ifbdb6b4c201560a97617e83d69bf9974f9411994 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: http://review.coreboot.org/10653 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>		2015-06-26 00:01:57 +02:00
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acpi	acpi/sata: add generic sata ssdt port generator	2015-06-07 01:24:47 +02:00
arch	acpi: bring back ability to link DSDT into ramstage	2015-06-23 21:19:02 +02:00
console	consoles: remove unused infrastructure	2015-05-26 19:02:54 +02:00
cpu	cpu: x86 port to 64bit	2015-06-20 18:16:54 +02:00
device	ddr3: add missing newline	2015-06-23 01:50:33 +02:00
drivers	Intel FSP 1.1: Move Kconfig comment inside 'if' block	2015-06-25 00:02:37 +02:00
ec	lenovo: Move pc_keyboard_init to h8 init.	2015-05-29 07:45:55 +02:00
include	cpu/x86: Add more MTRR symbols	2015-06-24 17:03:29 +02:00
lib	stage_cache: use cbmem init hooks	2015-06-09 22:06:40 +02:00
mainboard	pcengines/apu1: Remove unused ide.asl	2015-06-24 07:20:16 +02:00
northbridge	Kconfig: Move CBFS_SIZE into Mainboard menu	2015-06-23 09:42:44 +02:00
soc	soc/intel/common: Restrict common romstage/ramstage code to FSP	2015-06-26 00:01:57 +02:00
southbridge	amd/pi/hudson: Fill ROMSIG with 0xFF instead of 0	2015-06-25 04:06:59 +02:00
superio	superio: use common x86 code on x86-64	2015-06-22 07:36:09 +02:00
vendorcode	Intel vendorcode: Add FSP_SMBIOS_MEMORY_INFO_GUID	2015-06-24 17:02:58 +02:00
Kconfig	southbridge/intel: Create common IFD Kconfig and Makefile	2015-06-23 22:48:45 +02:00